1. Field of the Invention
The present invention relates to a memory control module and its associated control method, especially to a memory control module and the associated control method employing an LDPC (Low Density Parity Check) encoder/decoder concatenated with multiple BCH (Bose-Chaudhuri-Hocquenghem) encoders/decoders of different code lengths.
2. Description of Related Art
ECCs are widely used in digital data related systems or devices, such as communication systems, storage devices, etc., and the BCH code and the LDPC code are two common kinds of ECCs. FIG. 1A shows a prior art ECC encoder comprising an LDPC encoder concatenated with multiple BCH encoders. The ECC encoding circuit 100 includes n BCH encoders 110-1˜110-n and an LDPC encoder 120. Each BCH encoder 110 has the same code length. The BCH encoder 110 encodes the target data D0 to generate the data D1, which includes the target data D0 and multiple sets of BCH code parity check bits. Each set of BCH code parity check bits corresponds to a BCH encoder 110. Then the LDPC encoder 120 encodes the data D1 to generate the data D2, which includes the target data D0, the multiple sets of BCH code parity check bits and one set of LDPC code parity check bits. FIG. 1B shows an ECC decoder corresponding to the ECC encoder of FIG. 1A. The ECC decoder 150 includes n BCH decoders 160-1˜160-n, and an LDPC decoder 170. Likewise, the n BCH decoders 160 have the same code length, which is identical to the code length of the BCH encoders 110. The LDPC decoder 170 receives the data D2′, which corresponds to the data D2 but may contain several error bits, and corrects the error bits according to the set of LDPC code parity check bits included in the data D2′ to generate the data D1′. Each BCH decoder 160 decodes the data D1′ to correct the residual error bits. Finally, the data D0′ will be obtained, which will be identical to the target data D0 if all error bits are corrected.
The LDPC code has a shortcoming that there exists an error floor region in a figure illustrating the relationship between the bit error rate (BER) and the signal to noise ratio (SNR), which implies that the error correcting capability of the LDPC code is limited. Therefore, the ECC decoder 150 employs multiple BCH decoders 160 having different characteristics but the same code length to enhance the chance of successfully correcting the residual error bits. In addition to reducing the BER, such design also obscures the error floor region of the LDPC code. However, as the same code length is used by all BCH encoders 110 and all BCH decoders 160, each BCH encoder 110 or BCH decoder 160 processes the BCH code parity check bits of the same length, which limits the performance of the ECC encoding/decoding circuit.